The present invention relates to an integrated circuit arrangement having a cascoded current source and an adjusting circuit for adjusting the operating point of the cascoded current source.
A circuit arrangement based on internal knowledge of the applicant is shown in FIG. 1. The right part of FIG. 1 shows a cascoded current source 10, provided in an integrated circuit, which is formed in a way known per se from a first current source FET Q1 and a second current source FET Q2 (cascode). Further parts of the integrated circuit (not shown here) are connected to an output node 12. The current source 10 provides an output current Iout at this output node 12 (drain of the cascode FET Q2), whose value is a function of the properties of the FETs Q1, Q2 and of gate potentials Vg1, Vg2, which are provided by the adjusting circuit 20 shown in the left part of the figure and are applied to the gates of the FETs Q1 and Q2. It is essential for the operation of the current source 10 that the FETs Q1, Q2 always be operated in saturation, so that, in a way known per se, the output current Iout is barely a function of the voltage Vout at the output node. In other words, the current source 10 advantageously has a very high output impedance in this case. An FET is saturated when the drain-source voltage Vds is greater than the effective control voltage Vgt, Vgt being defined as the gate-source voltage minus the threshold voltage: Vgt=Vgsxe2x88x92Vth.
In comparison to a xe2x80x9csimple current sourcexe2x80x9d (without the cascode FET Q2), the current source 10 shown has a reduced output voltage swing, i.e., the permissible range for the output voltage Vout for operation of the current source is restricted by the drain-source voltage of Q2 in addition to the drain-source voltage of Q1. In order to keep this reduction of the voltage swing caused by the cascading as small as possible, the drain voltage Vx of the first current source FET Q1, which is equal to the source voltage of the second current source FET Q2, is to be adjusted as closely as possible to the saturation limit of Q1. Possible measures for this adjustment are explained in the following on the basis of FIGS. 1 and 2.
The left part of FIG. 1 shows the circuit 20 for operating point adjustment of the cascoded current source Q1, Q2. An FET M1, operated in the linear range, is used in the circuit in order to define the source voltage of cascode FETs M3, M4. This source voltage results as the voltage drop at FET M1, which is used here as a resistor element. Since the diode-switched FET M3 and the cascode M4 are identically dimensioned in regard to channel length and current density and both have the gate voltage Vg2, an equal source voltage, defined by M1, results at the cascodes M3, M4. For example, the FETs M3 and M4 may be identically dimensioned and each have a reference current Iref of equal size applied to them. This source voltage of the cascodes must be selected in this case in such a way that M2 is always sufficiently in saturation, i.e., its drain voltage (the source voltage of the cascodes) is always somewhat greater than its effective control voltage. The dimensioning of Q1 in comparison to M2 finally determines a xe2x80x9ctranslation ratioxe2x80x9d for the current Iout in relation to the current which flows through M2. The current densities in Q1 and M2 are identical. Correspondingly, if Q1 and M2 are dimensioned identically, Iout=Iref. The adjusting circuit 20 finally ensures that the source voltage Vx of the cascode Q2 is greater than the effective control voltage Vgt of the FET Q1.
FIG. 2 shows a further circuit 20 for operating point adjustment of a cascoded current source 10. The circuit generates the gate voltage Vg2 of cascodes M2, Q2 in another way, specifically in that the voltage which drops at a resistor R is added to the diode voltage of an FET M1 operated in saturation. The resistor R is selected in this case in such a way that the source voltage Vx of the cascode Q2 is in turn somewhat greater than the effective control voltage Vgt of M1. This voltage Vx is equal to the second gate potential Vg2 minus the gate-source voltage of M2. The circuit shown in FIG. 2 is known from European Patent Application EP 0 643 347 A1 and is described there as advantageous for achieving a high output impedance while simultaneously having relatively low current consumption.
In practice, the disadvantages described in the following result for the circuit arrangement shown in FIG. 2. In order to ensure the function of the cascoded current source 10, it is necessary for the drain voltage Vx of the first current source FET Q1 to be kept greater than its effective control voltage Vgt. In order to ensure this over the process variations during the manufacture of the integrated circuit and temperature variations during operation of the integrated circuit, a certain safety reserve is also typically added to the necessary drain voltage (Vgt). However, this safety reserve leads to yet a further restriction of the usable dynamic range (output voltage swing) of the current source, which is a grave disadvantage in consideration of the supply voltages for integrated circuits, which are becoming smaller and smaller.
It is therefore an object of the present invention to allow, in an integrated circuit, adjustment of the operating point of a cascoded current source, in which the voltage (Vx) on the drain of the first current source FET may be adjusted as near as possible to the saturation limit (Vgt) of this FET, independently of process variations and temperature variations.
This object is achieved by an integrated circuit arrangement having the features of Claim 1. The dependent claims relate to advantageous refinements of the present invention, which may each be provided alone or, especially advantageously, also combined with one another.
With the circuit arrangement according to the present invention, it is possible to adjust the voltage at the drain of the first current source FET (Q1) and/or the voltage at the source of the second current source FET (Q2) in such a way that, in regard to the process and temperature variations, these voltages follow the effective control voltage (Vgt) and keep a constant distance (safety reserve) to it. In particular, it is possible to greatly reduce the safety reserve and consequently increase the dynamic range of the overall circuit. For the circuits shown in FIG. 1 and FIG. 2 this xe2x80x9csynchronismxe2x80x9d of drain voltage Vx and effective control voltage (Vgt) is not provided or is only provided in a restricted way. Rather, in these circuits the threshold voltage Vth of the FETs always influences the drain voltage Vx of the current source 10. However, since the threshold voltage Vth has a completely different process and temperature dependence than the effective control voltage Vgt, synchronism may hardly be achieved. In the circuit shown in FIG. 2, the quality of adjustment is made even worse by the variation of the resistor R.
In the present invention, a reference stage is provided, formed by a pair of reference FETs, which are operated in saturation and using current densities which differ by a predetermined factor, so that reference gate potentials are provided at the gates of these reference FETs which are a function of the effective control voltages of the reference FETs, which form the basis of an optimized operating point adjustment of the current source. Furthermore, a processing stage is provided, into which the reference gate potentials are input in order to provide an adjustment potential on the basis of the predetermined factor, which is equal to the effective control voltage plus a predetermined additional voltage (safety reserve). This processing may be implemented in many ways, e.g., using an analog computer arrangement, e.g., using operational amplifiers. Finally, an output FET is provided which is connected on the source side to the adjustment potential and is dimensioned for current density at least approximately equal to the second current source FET and at whose gate the gate potential of the second current source FET (cascode) to be adjusted is provided. Therefore, independently of process and temperature variations, practically optimum gate potentials may be provided for the current source. In a preferred embodiment, the gate potential of the first reference FET is used as the gate potential of the first current source FET.
The measures specified in Claims 2, 3, and 4 are advantageous in regard to the precision and reliability of the operating point adjustment.
An especially simply constructed and reliable processing stage may be implemented as specified in Claim 5, in particular using one, more than one, or all of the embodiments specified in Claim 6.
The measures specified in Claim 7 advantageously lead to a double function of the output FET, specifically generating the necessary second gate potential and supplying an additional current for exact addition of an additional voltage to the threshold voltage at a resistor.